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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES6221/D Rev 1, 11/2002
Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
The Motorola MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.
MC100ES6221
LOW-VOLTAGE 1:20 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT DRIVER
* * * * * * * *
Features 1:20 differential clock fanout buffer 100 ps maximum device skew SiGe technology Supports DC to 2 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3V, -3.3V, 2.5V or -2.5V supply
TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A
Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics * Supports industrial temperature range
* Pin and function compatible to the MC100EP221
Functional Description The MC100ES6221 is designed for low skew clock distribution systems and supports clock frequencies up to 2 GHz. The device accepts two clock sources. The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If VBB is connected to the CLK0 or CLK1 input and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6221 can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the MC100EP221.
(c) Motorola, Inc. 2002
MC100ES6221
Q11 VCC
26 25 24 23 22 21
Q10
Q10
Q6
Q7
Q8
Q0 Q0
VCC
CLK0 CLK0

Q1 Q1 Q2 Q2 Q3 Q3
VCC Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0
40 41 42 43 44 45 46 47 48 49 50 51 52
39 38 37 36
35 34 33 32 31 30 29 28 27
Q9
Q11
Q6
Q7
Q8
Q9
Q12 Q12 Q13 Q13 Q14 Q14 Q15 Q15 Q16 Q16 Q17 Q17 VCC
VEE VCC
0 1

MC100ES6221
20 19 18 17 16 15 14
CLK1 CLK1
Q16 Q16 Q17 Q17
VEE
Q18 Q18 Q19 Q19 VBB
CLK_SEL
1
2
3
4
5
6
7
8
9
10
11
12 13
CLK_SEL
CLK0
CLK0
CLK1
CLK1
VCC
VCC
Q19
Q19
Q18
VBB
VEE
Figure 1. MC100ES6221 Logic Diagram Table 1. PIN CONFIGURATION
Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL Q[0-19], Q[0-19] VEEa VCC I/O Input Input Input Output Supply Supply Type ECL/PECL HSTL ECL/PECL ECL/PECL
Figure 2. 52-Lead Package Pinout (Top View)
Function Differential reference clock signal input Alternative differential reference clock signal input Reference clock input select Differential clock outputs Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation.
a.
VBB Output DC Reference voltage output for single ended ECL or PECL operation In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC).
Table 2. FUNCTION TABLE
Pin CLK_SEL 0 CLK0, CLK0 input pair is the reference clock. CLK0 can be driven by ECL or PECL compatible signals. 1 CLK1, CLK1 input pair is the reference clock. CLK1 can be driven by HSTL compatible signals.
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VEE
TIMING SOLUTIONS
Q18
MC100ES6221
Table 3. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
TFUNC Functional temperature range TA = -40 TJ = +110 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 4. General Specifications
Symbol VTT MM HBM CDM LU CIN JA, JB, JC TJ a. b. Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity Input Capacitance Thermal resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating junction temperatureb (continuous operation) MTBF = 9.1 years 200 2000 TBD 200 4.0 See Table 9 "Thermal Resistance" on page 9 0 110 Min Typ VCC - 2a Max Unit V V V V mA pF C/W Inputs Condition
C
Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase. Operating junction temperature impacts device life time. Maximum continues operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6221 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6221 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
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Table 5. PECL DC Characteristics (VCC = 2.5V 5% or VCC = 3.3V5%, VEE = GND, TJ = 0C to + 110C)
Symbol Characteristics Differential input voltageb Differential cross point voltagec Input Currenta Min Typ Max Unit Condition Clock input pair CLK0, CLK0a (PECL differential signals) VPP VCMR IIN 0.1 1.0 1.3 VCC-0.3 100 V V A Differential operation Differential operation VIN = VIL or VIN = VIH
Clock input pair CLK1, CLK1d (HSTL differential signals) VDIF Differential input voltagee VX VIH VIL IIN VIH VIL IIN VOH VOL IEEi Differential cross point voltagef Input high voltage Input low voltage Input Current
0.2 0 VX+0.1 VX-0.7 0.68 - 0.9
1.4 VCC-0.7 VX+0.7 VX-0.1 100
V V V V A VIN = VX 0.2V
Clock inputs (PECL single ended signals) Input voltage high Input voltage low Input Currentg VCC-1.165 VCC-1.810 VCC-0.880 VCC-1.475 100 V V A VIN = VIL or VIN = VIH IOH = -30 mAh IOL = -5 mAh VEE pins
PECL clock outputs (Q0-19, Q0-19) Output High Voltage Output Low Voltage VCC-1.1 VCC-1.9 VCC-1.005 VCC-1.705 84 VCC-0.7 VCC-1.4 160 V V
Supply current and VBB Maximum Quiescent Supply Current without output termination current mA
a. b. c. d. e. f. g. h. i. j.
VBB Output reference voltage (fref < 1.0 GHz)j VCC-1.42 VCC-1.20 V IBB = 0.4 mA The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. Inputs have internal pullup/pulldown resistors which affect the input current. Equivalent to a termination of 50W to VTT. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT )/Rload + (VOL - V TT )/Rload + IEE. Using VBB to bias unused single-ended inputs is recommended only up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential input signals should be used with the MC100ES6221.
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MC100ES6221
Table 6. ECL DC Characteristics (VEE = -2.5V 5% or VEE = -3.3V5%, VCC = GND, TJ = 0C to + 110C)
Symbol Characteristics Min Typ Max Unit Condition Clock input pair CLK0, CLK0 (ECL differential signals) VPP Differential input voltagea VCMR IIN VIH VIL IIN VOH VOL Differential cross point voltageb Input Currenta
0.1 VEE+1.0
1.3 -0.3 100
V V A
Differential operation Differential operation VIN = VIL or VIN = VIH
Clock inputs (ECL single ended signals) Input voltage high Input voltage low Input Currentc -1.165 -1.810 -0.880 -1.475 100 V V A VIN = VIL or VIN = VIH IOH = -30 mAd IOL = -5 mAd VEE pins
ECL clock outputs (Q0-A19, Q0-A19) Output High Voltage Output Low Voltage -1.1 -1.9 -1.005 -1.705 -0.7 -1.4 V V
Supply current and VBB IEEe Maximum Quiescent Supply Current without output termination current a. b. c. d. e. f.
84
160
mA
VBB Output reference voltage (fref < 1.0 GHz)f -1.42 -1.20 V IBB = 0.4 mA VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Inputs have internal pullup/pulldown resistors which affect the input current. Equivalent to a termination of 50W to VTT. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH - VTT )/Rload + (VOL - V TT )/Rload + IEE. VBB can be used to bias unused single-ended inputs up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential signals should be used with the MC100ES6221.
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MC100ES6221
Table 7. AC Characteristics (ECL: VEE = -3.3V (PECL: VCC = 3.3V
Symbol Characteristics
5% or VCC = 2.5V 5%, VEE = GND, TJ = 0C to + 110C)a
Min Typ
5% or VEE = -2.5V 5%, VCC = GND) or
Max Unit Condition
Clock input pair CLK0, CLK0 (PECL or ECL differential signals) VPP Differential input voltageb (peak-to-peak) VCMR fCLK tPD Differential input crosspoint voltagec Input Frequency Propagation Delay CLK0 to Q0-19 PECL ECL
0.2 1.0 VEE+1.0 0 400 540
1.3 VCC-0.3 -0.3V 2000 670
V V V MHz ps Differential Differential
Clock input pair CLK1, CLK1 (HSTL differential signals) VDIF Differential input voltaged (peak-to-peak) VX fCLK tPD VO(P-P) Differential input crosspoint voltagee Input Frequency Propagation Delay CLK1 to Q0-19
0.2 0.1 0 650 780 0.68-0.9
1.3 VCC-1.0 1000 950
V V MHz ps Differential Differential
PECL/ECL clock outputs (Q0-19, Q0-19) Differential output voltage (peak-to-peak) fO < 1.0 GHz fO < 2.0 GHz Output-to-output skew Output-to-output skew (part-to-part) using CLK0 using CLK1 parts at one given TJ, VCC, fref tJIT(CC) tSK(P) DCQ Output cycle-to-cycle jitter Output pulse skewf Output Duty Cycle fREF < 0.1 GHz fREF < 1.0 GHz 49.5 45.0 30 50 50 270 300 250 TBD 50 50.5 55.0 ps ps ps ps ps % % DCREF = 50% DCREF = 50% 375 TDB 630 250 50 100 V V ps Differential Differential
tsk(O) tsk(PP)
tr, tf Output Rise/Fall Time 50 350 ps 20% to 80% AC characteristics apply for parallel output termination of 50 to VTT. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. c. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. d. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. Only applicable to CLKB. e. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the V DIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. f. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. a. b.
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TIMING SOLUTIONS
MC100ES6221
Differential Pulse Generator Z = 50W
ZO = 50
ZO = 50
RT = 50 VTT
DUT MC100ES6221
RT = 50 VTT
Figure 3. MC100ES6221 AC test reference
CLKN CLKN QX QX tPD (CLKN to QX)
VPP=0.8V
VCMR=VCC-1.3V
Figure 4. MC100ES6221 AC reference measurement waveform
TIMING SOLUTIONS
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MOTOROLA
MC100ES6221
APPLICATIONS INFORMATION
Understanding the junction temperature range of the MC100ES6221 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6221, the MC100ES6221 is specified, characterized and tested for the junction temperature range of TJ=0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this datasheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Assuming a thermal resistance (junction to ambient) of 17 C/W (2s2p board, 200 ft/min airflow, see Table 9 on page 9) and a typical power consumption of 1148 mW (all outputs terminated 50 ohms to V TT, V CC =3.3V, frequency independent), the junction temperature of the MC100ES6221 is approximately TA + 21 C, and the minimum ambient temperature in this example case calculates to -21 C (the maximum ambient temperature is 89 C. See Table 8). Exceeding the minimum junction temperature specification of the MC100ES6221 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6221 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Table 8. Ambient temperature ranges (Ptot = 1148mW)
Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 20 C/W 18 C/W 17 C/W 16 C/W 15 C/W TA, mina -23 C -21 C -20 C -18 C -17 C TA, max 87 C 89 C 90 C 92 C 93 C
Maintaining Lowest Device Skew The MC100ES6221 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of max. 270 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6221 is a mixed analog/digital product. The differential architecture of the MC100ES6221 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
VCC 33...100 nF 0.1 nF
VCC MC100ES6221
Figure 5. VCC Power Supply Bypass
a. The MC100ES6221 device function is guaranteed from TA=-40 C to TJ=110 C
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TIMING SOLUTIONS
MC100ES6221
APPLICATIONS INFORMATION
Using the thermally enhanced package of the MC100ES6221 The MC100ES6221 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the leadframe is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6221 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6221. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6221 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6. "Recommended thermal land pattern", providing an efficient heat removal path.
all units mm
recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter
Figure 7. Recommended solder mask openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: Table 9. Thermal Resistancea
ConvectionLFPM Natural 100 200 400 800 RTHJAb C/W 20 18 17 16 15 RTHJAc C/W 48 47 46 43 41 4e 29f RTHJC C/W RTHJBd C/W
4.8
4.8
Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter
Exposed pad land pattern
Figure 6. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7. "Recommended solder mask openings" shows a recommend solder mask opening with respect to the
a. Applicable for a 3 x 3 thermal via array b. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5 c. Junction to ambient, single layer test board, per JESD51-3 d. Junction to board, four conductor layer test board (2S2P) per JESD 51-8 e. Junction to exposed pad f. Junction to top of package It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6221 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers.
TIMING SOLUTIONS
9
I I I IIIIIIIIII IIIIIIII IIII I IIIII II IIIIIIIIII IIIIIIIIII I II II II II II II II II II II II II IIII II II II II II IIII II II II II II IIII II II II I I IIIII II IIII II IIIIIIIII IIIIIIII IIIIIII IIIIIII
0.2 1.0 0.2 4.8 1.0
all units mm
4.8
Exposed pad land pattern
I IIIII IIIIIIIIII IIIIIIIIII I IIIII IIIIIIIIII IIIIIIIIII II II IIII I I II II IIII I I II II I I II II IIII I II II IIII I II IIIIIIII I IIIIIIII I IIIIIIIII IIIIIII IIIIIIII IIIIII
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MC100ES6221
OUTLINE DIMENSIONS
TB SUFFIX PLASTIC LQFP PACKAGE EXPOSED PAD CASE 1336A-01 ISSUE O
4X 4X 13 TIPS
0.2 H A-B D D
PIN 1 INDEX 1 52 40 39
0.2 C A-B D 7 1.5 1.3 0.05 B 10 6 12 5 6 6 4 X 4 VIEW AA 0.20 R 0.08
(0.2) 0 MIN 0.20 R 0.08
0.25
GAUGE PLANE
A
0.20 0.05
0.75 0.45 (1)
7 0
13 14 26
27
X=A, B OR D
5
6 64 10 6 12 4
C L
B B VIEW Y
48X
0.65
H 1.7 MAX
4X
(12 )
VIEW AA
52X
8
(0.3)
BASE METAL
0.1 C 8 J C
SEATING PLANE 52X
0.08
M
0.40 0.22 5 C A-B D
4X
(12 )
J
PLATING
0.20 0.09
4.78 4.58
4.78 4.58
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSION TO BE DETERMINED AT SEATING PLANE C. 5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. THIS DIMENSION IS MAXIMUM PLASTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP.
EXPOSED PAD VIEW Y
VIEW J-J
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CCCC EEEE CCCC EEEE CCCC EEEE CCCC EEEE
0.35 0.20 SECTION B-B
0.16 0.07
8
8
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MC100ES6221
NOTES
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MC100ES6221
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
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MC100ES6221/D TIMING SOLUTIONS

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